To increase the timing margin allowed for data to be transferred in a synchronous transfer mode in a semiconductor integrated circuit, techniques have been established that provide a delay time to a given signal. With recent advances in data transfer speed, there has developed a need for a delayed signal generating circuit that can adjust the delay time in finer steps and with higher accuracy.
FIG. 1 is a circuit configuration diagram of a prior art delayed signal generating circuit disclosed in patent document 1 cited below. The delayed signal generating circuit 90 includes N delay elements 91 for delaying a reference clock, S delay elements 92 for delaying a signal A, i.e., the target signal to be delayed, a latch circuit 93 which latches the signal stored in each delay element 91 at the falling edge of the reference clock, a decision circuit 94 which detects from the signal latched in the latch circuit 93 the number of delay elements 91 whose signals are “Hi”, and a selector 95 which selects, in accordance with a control signal from the decision circuit 94, the delay element 92 from which a delayed version of the signal A is to be extracted, wherein the number of delay elements through which the target signal is to be delayed is adjusted in accordance with the ratio of the pulse duration of the reference clock to the delay time of each delay element, thereby avoiding the effects that temperature variations or voltage variations may have on the amount of delay.
Patent document 2 cited below discloses a synchronous type semiconductor storage device equipped with an initial delay control value determining circuit that determines the initial value of the delay control value by detecting how far a pulse signal corresponding to one clock cycle of an external clock signal propagates through a variable delay circuit within a predetermined time.
Further, patent document 3 cited below discloses a clock regenerating circuit having a control circuit that detects the number of delay stages in a delay circuit necessary for synchronization by comparing the phase of an external clock with the phases of a plurality of reference clocks.
Patent document 1: Japanese Unexamined Patent Publication No. 2003-23343
Patent document 2: Japanese Unexamined Patent Publication No. H11-306757
Patent document 3: Japanese Unexamined Patent Publication No. 2000-59209